SKU Details
SKU000909
Motorola MC100LVEL14 clock fanout
Locations
| Bin | Identifier | Quantity | Type |
|---|
Properties
name
Motorola MC100LVEL14 clock fanout
item_type
Electronic component
component_function
Buffer / line driver
manufacturer
Motorola
part_number
MC100LVEL14DW
channel_count
5
package
SMD (other)
logic_family
100LVEL ECL / LVPECL
signal_direction
Unidirectional
independent_enable_groups
1
output_enable_behavior
Common synchronous EN prevents runt pulses; disabling holds Q outputs low. SEL chooses differential CLK or single-ended scan clock.
supply_voltage_min
{"value":3,"unit":"V"}
supply_voltage_max
{"value":3.8,"unit":"V"}
specification_basis
Exact-part datasheet
datasheet_url
https://www.onsemi.com/download/data-sheet/pdf/mc100lvel14-d.pdf
electrical_rating_conditions
Supply fields describe positive PECL operation with VEE = 0 V. Alternatively NECL uses VCC = 0 V and VEE = -3.0 to -3.8 V. Differential ECL outputs require appropriate termination; not directly interchangeable with CMOS/TTL clock buffers. Current onsemi documentation covers the legacy Motorola part; do not infer Pb-free G suffix for these marked DW parts.
Description
1-to-5 low-skew differential clock-distribution IC in 20-pin wide-body SOIC (DW), ten leads per side. Photos show Motorola logo and top marking 100LVEL14; bag explicitly MC100LVEL14DW. Five differential output pairs, selectable differential clock or scan/test clock input, common synchronous enable, VBB single-ended reference. Condition/function untested. Reference datasheet: https://www.onsemi.com/download/data-sheet/pdf/mc100lvel14-d.pdf
Created through automation
true
Automation source or version
Inventory Assistant 0.1.0+codex.20260919214048; gpt-6.1-sol (host-reported)
package_designation
SOIC-20 wide-body (DW)
terminal_count
20
Derived Batches
- BAT000934Motorola MC100LVEL14 clock fanoutName from SKU
Codes
MC100LVEL14DW
Associated